The Logic Built-In Self Test (LBIST) test methodology is being increasingly adopted as a complement to scan based structural testing. In Logic BIST, additional hardware is added to the chip to be tested. This additional hardware comprises a random pattern generator (typically a Linear Feedback Shift Register or LFSR) and a test response analyzer (typically a Multiple Input Signature Register or MISR). During Logic BIST, pseudo random patterns are applied to the chip under test (CUT) through the scan chains using the on chip pattern generator and the response of the CUT to these patterns is compacted into a test signature in the on chip test response analyzer. Since Logic BIST only applies pseudo random patterns, it cannot achieve the same fault coverage as a scan based structural test set generated using an Automatic Test Pattern Generation (ATPG) tool. However, since Logic BIST only applies pseudo random patterns, it has a significant advantage over scan based structural test: it needs very minimal support from the external test environment (incidentally, this is why the technique is named Built in Self Test). Ordinarily, the only interaction with the outside test environment is at the beginning of testing when an initial seed for the pseudo random pattern generator along with a start signal is provided, and at the end of testing when the test signature in the test response analyzer is compared with a golden value. For this reason, Logic BIST can be used to apply millions of test patterns to the CUT with the aim of catching obscure, unexpected and hard to model issues. These can include un-modelled timing marginalities, crosstalk, power defects that have unstable behaviour, etc. With increasing design complexities and a fabrication process that is flirting with the limits imposed by the laws of physics, accounting for such issues during design time is becoming extremely difficult. To handle such unexpected issues during testing, Logic BIST has been increasingly adopted as a preferred test technique.
Due to the above trend, it has become more important to devise effective diagnosis methodologies for Logic BIST. The main challenge with such a methodology is that since the test response is compacted into the test response analyzer, the actual failing scan cells are not known, which is what conventional diagnosis algorithms use to determine the most likely location within the circuit from which the failure originated. Several solutions to this problem have been proposed. However, all of these conventional solutions place unreasonable requirements on Logic BIST design, like significant additional hardware, multiple test applications, etc.
In current practice, the diagnosis of chips that fail LBIST tests is performed using the following procedure:                a. The Logic BIST test patterns that failed are identified by comparing the test signature at the end of every pattern to the expected signature at that point and thereafter resetting the test response analyzer to the correct expected value to make the failing patterns independent;        b. Special bypass patterns are generated corresponding to each of the Logic BIST failing tests identified above; and        c. The chip is retested with these bypass patterns with the chip in a special bypass mode in which the scan chains are accessed directly at the chip pins without having to go through the test response analyzer or random pattern generator. This way the actual failing scan cells for each failing pattern are identified. Hereafter, conventional logic diagnosis can be used.        
The above diagnostic method is very cumbersome since it requires separate bypass test patterns to be generated and applied. Moreover, in many cases, it may be impossible to get bypass patterns that are exactly the same as the failing Logic BIST tests, in which case there may be a situation in which a Logic BIST pattern fails but the corresponding bypass pattern does not fail.
Recently, a new technique called “signature based diagnosis for Logic BIST” has been introduced that does not require patterns to be re-applied in bypass mode and can perform diagnosis from only the failing test signature itself, thus significantly reducing the complexity of LBIST diagnosis. Signature based diagnosis methodologies provide attractive methods for diagnosing Logic BIST failures because they eliminate most of the complexity associated with the traditional approach to logic BIST diagnostics while achieving similar diagnosis resolution. Embodiments of the signature based diagnosis methodology are described, for example, in W.-T. Cheng, M. Sharma, T. Rinderknecht, L. Lai and C. Hill, “Signature Based Diagnosis for Logic BIST” in Proc. Intl. Test Conf., 2006, and United States Published Patent Application No. 2007/0100586, filed Oct. 20, 2006, and entitled “Direct Fault Diagnostics Using Per-Pattern Compactor Signatures,” both of which are incorporated herein by reference. One issue that can be encountered during application of the technique is that since only the failing test signature is known, a large number of potentially failing locations may need to be simulated before finding the ones that best explain the failing behaviour. This will directly translate into undesirably long processing time for logic diagnosis.